Samuel K. Moore

3 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. Intel’s Xeon 6 CPUs are made using the new Intel 3 manufacturing process. Last week at VLSI Symposium, Intel detailed the manufacturing process that will form the foundation of its foundry service for high-performance data center customers. For the same power consumption, the Intel 3 process results in an 18 percent performance gain over the previous process, Intel 4. On the company’s roadmap, Intel

4 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. Nvidia’s predominance in GPU systems for AI training continues in the latest MLPerf set of AI benchmarks. For years, Nvidia has dominated many machine learning benchmarks, and now there are two more notches in its belt. MLPerf, the AI benchmarking suite sometimes called “the Olympics of machine learning,” has released a new set of training tests to help make more and better apples-to-apples comparisons

7 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. Imec managed to make 3D connections between chips placed once every 2 micrometers. Researchers at the IEEE Electronic Components and Technology Conference (ECTC) last week pushed the state of the art in a technology that is becoming critical to cutting-edge processors and memory. Called hybrid bonding, the technology stacks two or more chips atop each other in the same package, allowing chipmakers to increase

3 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. TSMC’s wafer-scale integration tech is the key to Tesla’s Dojo AI training accelerator. A more advanced version is coming in 2027. At TSMC’s North American Technology Symposium on Wednesday, the company detailed both its semiconductor technology and chip-packaging technology road maps. While the former is key to keeping the traditional part of Moore’s Law going, the latter could accelerate a trend toward processors made

3 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. Intel’s Gaudi 3 is packaged with eight high-bandwidth memory chips. Although the race to power the massive ambitions of AI companies might seem like it’s all about Nvidia, there is a real competition going in AI accelerator chips. The latest example: At Intel’s Vision 2024 event this week in Phoenix, Ariz., the company gave the first architectural details of its third-generation AI accelerator, Gaudi

4 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. It’s H200’s world, we’re only inferencing in it. Times change, and so must benchmarks. Now that we’re firmly in the age of massive generative AI, it’s time to add two such behemoths, Llama 2 70B and Stable Diffusion XL, to MLPerf’s inferencing tests. Version 4.0 of the benchmark tests more than 8,500 results from 23 submitting organizations. As has been the case from the

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17 Mar 2024 3 min read The newly announced Blackwell GPUs are two 800-square-millimeter silicon dies joined along one edge. Today at Nvidia’s developer conference, GTC 2024, the company revealed its next GPU, the B200. The B200 is capable of delivering four times the training performance, up to 30 times the inference performance, and up to 25 times better energy efficiency, compared to its predecessor, the Hopper H100 GPU. Based on the new Blackwell architecture,