Samuel K. Moore

5 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. Tahir Ghani—known to his colleagues at Intel as “Mr. Transistor”—says that implementing the tech for 45-nanometer nodes was the riskiest moment of his career. Intel Corp. It says something about your career at a company that makes hundreds of trillions of transistors every day when your nickname is “Mr. Transistor.” That’s what colleagues sometimes call Tahir Ghani, a senior fellow and director of process

5 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. Intel skipped commercializing its 20A manufacturing process in favor of the next generation 18A. Intel Foundry I like to think I can learn something about our readers from the list of most read semiconductor articles. What I think I’ve learned from this year’s list is that you are as obsessed as I am with packing more and more computing power into less and less

3 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. Do you see TSMC’s new transistors at the bottom? Me neither. TSMC described its next generation transistor technology this week at the IEEE International Electron Device Meeting (IEDM) in San Francisco. The N2, or 2-nanometer, technology is the semiconductor foundry giant’s first foray into a new transistor architecture, called nanosheet or gate-all-around. Samsung has a process for manufacturing similar devices, and both Intel and

4 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. Peter Blottman Photography Machine learning chips that use analog circuits instead of digital ones have long promised huge energy savings. But in practice they’ve mostly delivered modest savings, and only for modest-sized neural networks. Silicon Valley startup Sageance says it has the technology to bring the promised power savings to tasks suited for massive generative AI models. The startup claims that its systems will

4 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. Nvidia posted benchmark results for its Blackwell architecture chips. Annabelle Chih/Bloomberg/Getty Images Nvidia, Oracle, Google, Dell and 13 other companies reported how long it takes their computers to train the key neural networks in use today. Among those results were the first glimpse of Nvidia’s next generation GPU, the B200, and Google’s upcoming accelerator, called Trillium. The B200 posted a doubling of performance on

2 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. AnnaStills/iStock Finished chips coming in from the foundry are subject to a battery of tests. For those destined for critical systems in cars, those tests are particularly extensive and can add 5 to 10 percent to the cost of a chip. But do you really need to do every single test? Engineers at NXP have developed a machine-learning algorithm that learns the patterns of

4 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. The NSTC’s EUV center will be at the Albany Nanotech Complex, where IBM already does lithography research. Last week the organization tasked with running the the biggest chunk of U.S. CHIPS Act’s US $13 billion R&D program made some significant strides: The National Semiconductor Technology Center (NSTC) released a strategic plan and selected the sites of two of three planned facilities and released a

There’s a certain sameness to spaces meant for tech startups: flexible cubicle arrangements, glass-encased executive offices, whiteboard walls awaiting equations and ideas, basement laboratories for the noisier and more dangerous parts of the process. In some ways the home of Ideal Semiconductor on the campus of Lehigh University, in Bethlehem, Penn., is just like that. The most noticeable difference is a life-size statue of 18th-century inventor and electricity enthusiast Benjamin Franklin seated on the bench

9 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. Big-name makers of processors, especially those geared toward cloud-based AI, such as AMD and Nvidia, have been showing signs of wanting to own more of the business of computing, purchasing makers of software, interconnects, and servers. The hope is that control of the “full stack” will give them an edge in designing what their customers want. Amazon Web Services (AWS) got there ahead of

3 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. Intel’s Xeon 6 CPUs are made using the new Intel 3 manufacturing process. Last week at VLSI Symposium, Intel detailed the manufacturing process that will form the foundation of its foundry service for high-performance data center customers. For the same power consumption, the Intel 3 process results in an 18 percent performance gain over the previous process, Intel 4. On the company’s roadmap, Intel