Samuel K. Moore

4 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. Nvidia posted benchmark results for its Blackwell architecture chips. Annabelle Chih/Bloomberg/Getty Images Nvidia, Oracle, Google, Dell and 13 other companies reported how long it takes their computers to train the key neural networks in use today. Among those results were the first glimpse of Nvidia’s next generation GPU, the B200, and Google’s upcoming accelerator, called Trillium. The B200 posted a doubling of performance on

2 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. AnnaStills/iStock Finished chips coming in from the foundry are subject to a battery of tests. For those destined for critical systems in cars, those tests are particularly extensive and can add 5 to 10 percent to the cost of a chip. But do you really need to do every single test? Engineers at NXP have developed a machine-learning algorithm that learns the patterns of

4 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. The NSTC’s EUV center will be at the Albany Nanotech Complex, where IBM already does lithography research. Last week the organization tasked with running the the biggest chunk of U.S. CHIPS Act’s US $13 billion R&D program made some significant strides: The National Semiconductor Technology Center (NSTC) released a strategic plan and selected the sites of two of three planned facilities and released a

There’s a certain sameness to spaces meant for tech startups: flexible cubicle arrangements, glass-encased executive offices, whiteboard walls awaiting equations and ideas, basement laboratories for the noisier and more dangerous parts of the process. In some ways the home of Ideal Semiconductor on the campus of Lehigh University, in Bethlehem, Penn., is just like that. The most noticeable difference is a life-size statue of 18th-century inventor and electricity enthusiast Benjamin Franklin seated on the bench

9 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. Big-name makers of processors, especially those geared toward cloud-based AI, such as AMD and Nvidia, have been showing signs of wanting to own more of the business of computing, purchasing makers of software, interconnects, and servers. The hope is that control of the “full stack” will give them an edge in designing what their customers want. Amazon Web Services (AWS) got there ahead of

3 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. Intel’s Xeon 6 CPUs are made using the new Intel 3 manufacturing process. Last week at VLSI Symposium, Intel detailed the manufacturing process that will form the foundation of its foundry service for high-performance data center customers. For the same power consumption, the Intel 3 process results in an 18 percent performance gain over the previous process, Intel 4. On the company’s roadmap, Intel

4 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. Nvidia’s predominance in GPU systems for AI training continues in the latest MLPerf set of AI benchmarks. For years, Nvidia has dominated many machine learning benchmarks, and now there are two more notches in its belt. MLPerf, the AI benchmarking suite sometimes called “the Olympics of machine learning,” has released a new set of training tests to help make more and better apples-to-apples comparisons

7 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. Imec managed to make 3D connections between chips placed once every 2 micrometers. Researchers at the IEEE Electronic Components and Technology Conference (ECTC) last week pushed the state of the art in a technology that is becoming critical to cutting-edge processors and memory. Called hybrid bonding, the technology stacks two or more chips atop each other in the same package, allowing chipmakers to increase

3 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. TSMC’s wafer-scale integration tech is the key to Tesla’s Dojo AI training accelerator. A more advanced version is coming in 2027. At TSMC’s North American Technology Symposium on Wednesday, the company detailed both its semiconductor technology and chip-packaging technology road maps. While the former is key to keeping the traditional part of Moore’s Law going, the latter could accelerate a trend toward processors made

3 min read Samuel K. Moore is IEEE Spectrum’s semiconductor editor. Intel’s Gaudi 3 is packaged with eight high-bandwidth memory chips. Although the race to power the massive ambitions of AI companies might seem like it’s all about Nvidia, there is a real competition going in AI accelerator chips. The latest example: At Intel’s Vision 2024 event this week in Phoenix, Ariz., the company gave the first architectural details of its third-generation AI accelerator, Gaudi