Cadence’s demo is impressive not only for the transfer rate, but for the low bit error rate (BER) and also for the way in which it was achieved. The company says that its demo was performed using “off-the-shelf optical connectors” without retimers, and that over the two days without breaks, it achieved a bit error rate of about 3.6E-8, or around 1 error in every 280 million transmitted bits.
That’s particularly impressive in the context that the PCIe 7.0 draft specification only mandates an error rate of no worse than 1E-6, or one error in every million bits. Cadence’s IP has clearly far exceeded this requirement by a margin sufficient that commonplace Reed-Solomon Forward Error Correction (RS-FEC) can deal with the errors.
This wasn’t the only demo that Cadence had on the floor at SIG DevCon ’24; the company also demonstrated PCIe 7.0 over a conventional interconnect as well as many different PCIe 6.0 implementations. Of course, the optical PCIe 7.0 live demo, the first of its kind in the world, was the star of the show.
If you’re thinking back to our recent coverage and thinking that 128 GT/sec sounds low, remember that we’re talking about bit-level transfers on a single link. 128 GT/sec is the unidirectional transfer rate of PCIe 7.0; that gives a theoretical bandwidth of 16 GB/second, which becomes 256 GB/sec on an x16 link and thus 512 GB/second bidirectionally. As such, this is the same speed as that previous announcement.
PCI-SIG hasn’t even ratified the final PCIe 7.0 specification yet; that’s not expected to happen until early next year. With these early implementations, though, we could start to see devices based on PCIe 7.0 around that time, at least in the hyperscale enterprise market. Gamer plebeians like your author will have to wait a few generations before PCIe 7.0 makes its way to our systems.